System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LMC_HOME C:\Xilinx\ISE\smartmodel\nt\installed_nt C:\Xilinx\ISE\smartmodel\nt\installed_nt C:\Xilinx\ISE\smartmodel\nt\installed_nt C:\Xilinx\ISE\smartmodel\nt\installed_nt
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.3\ISE_DS\common\bin\nt;
C:\Xilinx\12.3\ISE_DS\common\lib\nt;
d:\ispLEVER_Classic1_6\ispcpld\bin;
d:\ispLEVER_Classic1_6\ispFPGA\bin\nt;
C:\Xilinx\ISE\bin\nt;
C:\Xilinx\ISE\lib\nt;
C:\Xilinx\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\ATI Technologies\ATI Control Panel;
C:\Program Files\Total Commander Ultima Prime5\PLUGINS\Library;
C:\Xilinx\bin\nt;
C:\PBWin80\BIN;
C:\PBWin\BIN;
F:\backup\MPLAB\MPLAB C32 Suite\bin;
C:\Program Files\HI-TECH Software\PICC\9.83\bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools\WinNT;
C:\Program Files\Microsoft Visual Studio\Common\MSDev98\Bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools;
C:\Program Files\Microsoft Visual Studio\VC98\bin		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.3\ISE_DS\common\bin\nt;
C:\Xilinx\12.3\ISE_DS\common\lib\nt;
d:\ispLEVER_Classic1_6\ispcpld\bin;
d:\ispLEVER_Classic1_6\ispFPGA\bin\nt;
C:\Xilinx\ISE\bin\nt;
C:\Xilinx\ISE\lib\nt;
C:\Xilinx\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\ATI Technologies\ATI Control Panel;
C:\Program Files\Total Commander Ultima Prime5\PLUGINS\Library;
C:\Xilinx\bin\nt;
C:\PBWin80\BIN;
C:\PBWin\BIN;
F:\backup\MPLAB\MPLAB C32 Suite\bin;
C:\Program Files\HI-TECH Software\PICC\9.83\bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools\WinNT;
C:\Program Files\Microsoft Visual Studio\Common\MSDev98\Bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools;
C:\Program Files\Microsoft Visual Studio\VC98\bin		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.3\ISE_DS\common\bin\nt;
C:\Xilinx\12.3\ISE_DS\common\lib\nt;
d:\ispLEVER_Classic1_6\ispcpld\bin;
d:\ispLEVER_Classic1_6\ispFPGA\bin\nt;
C:\Xilinx\ISE\bin\nt;
C:\Xilinx\ISE\lib\nt;
C:\Xilinx\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\ATI Technologies\ATI Control Panel;
C:\Program Files\Total Commander Ultima Prime5\PLUGINS\Library;
C:\Xilinx\bin\nt;
C:\PBWin80\BIN;
C:\PBWin\BIN;
F:\backup\MPLAB\MPLAB C32 Suite\bin;
C:\Program Files\HI-TECH Software\PICC\9.83\bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools\WinNT;
C:\Program Files\Microsoft Visual Studio\Common\MSDev98\Bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools;
C:\Program Files\Microsoft Visual Studio\VC98\bin		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.3\ISE_DS\common\bin\nt;
C:\Xilinx\12.3\ISE_DS\common\lib\nt;
d:\ispLEVER_Classic1_6\ispcpld\bin;
d:\ispLEVER_Classic1_6\ispFPGA\bin\nt;
C:\Xilinx\ISE\bin\nt;
C:\Xilinx\ISE\lib\nt;
C:\Xilinx\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\ATI Technologies\ATI Control Panel;
C:\Program Files\Total Commander Ultima Prime5\PLUGINS\Library;
C:\Xilinx\bin\nt;
C:\PBWin80\BIN;
C:\PBWin\BIN;
F:\backup\MPLAB\MPLAB C32 Suite\bin;
C:\Program Files\HI-TECH Software\PICC\9.83\bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools\WinNT;
C:\Program Files\Microsoft Visual Studio\Common\MSDev98\Bin;
C:\Program Files\Microsoft Visual Studio\Common\Tools;
C:\Program Files\Microsoft Visual Studio\VC98\bin
XILINX C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   LCD.prj  
-ifmt   mixed MIXED
-ofn   LCD  
-ofmt   NGC NGC
-p   xc3s400-5-tq144  
-top   LCD  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 2 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   YES NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   100000 500
-bufg   8 8
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   True AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc3s400-tq144-5 None
-uc   Source/Mono_LCD.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xe Placer Extra Effort Map CONTINUE  
-ir Use RLOC Constraints OFF OFF
-logic_opt Combinatorial Logic Optimization TRUE FALSE
-t Starting Placer Cost Table (1-100) Map 1 0
-cm Optimization Strategy (Cover Mode) speed area
-intstyle   ise None
-o   LCD_map.ncd None
-pr Pack I/O Registers/Latches into IOBs b off
-p   xc3s400-tq144-5 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-t   1 1
-xe   n None
-intstyle   ise  
-ol Place & Route Effort Level (Overall) std std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Pentium(R) 4 CPU 3.00GHz/2993 MHz Intel(R) Pentium(R) 4 CPU 3.00GHz/2993 MHz Intel(R) Pentium(R) 4 CPU 3.00GHz/2993 MHz Intel(R) Pentium(R) 4 CPU 3.00GHz/2993 MHz
Host tutijo-d3140627 tutijo-d3140627 tutijo-d3140627 tutijo-d3140627
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Szervizcsomag 3 (build 2600) Szervizcsomag 3 (build 2600) Szervizcsomag 3 (build 2600) Szervizcsomag 3 (build 2600)