LCD Project Status (09/19/2012 - 18:55:01)
Project File: Mono_LCD_Spartan3.xise Parser Errors: No Errors
Module Name: LCD Implementation State: Programming File Generated
Target Device: xc3s400-5tq144
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
2650 Warnings (89 new)
Design Goal: Minimum Runtime
  • Routing Results:
All Signals Completely Routed
Design Strategy: Feco1
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 2,434 7,168 33%  
Number of 4 input LUTs 5,590 7,168 77%  
Number of occupied Slices 3,243 3,584 90%  
    Number of Slices containing only related logic 3,243 3,243 100%  
    Number of Slices containing unrelated logic 0 3,243 0%  
Total Number of 4 input LUTs 5,865 7,168 81%  
    Number used as logic 5,579      
    Number used as a route-thru 275      
    Number used as Shift registers 11      
Number of bonded IOBs 96 97 98%  
    IOB Flip Flops 157      
Number of RAMB16s 16 16 100%  
Number of MULT18X18s 6 16 37%  
Number of BUFGMUXs 3 8 37%  
Average Fanout of Non-Clock Nets 3.57      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSze szept. 19 18:02:31 20120150 Warnings (89 new)41 Infos (0 new)
Translation ReportCurrentSze szept. 19 18:30:46 2012000
Map ReportCurrentSze szept. 19 18:34:55 201202462 Warnings (0 new)4 Infos (0 new)
Place and Route ReportCurrentSze szept. 19 18:39:26 201202 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSze szept. 19 18:39:45 2012005 Infos (0 new)
Bitgen ReportCurrentSze szept. 19 18:54:58 2012036 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportOut of DateP aug. 5 12:30:10 2011
Locked Pin ConstraintsOut of DateV aug. 21 08:09:47 2011
WebTalk Log FileCurrentSze szept. 19 18:55:01 2012

Date Generated: 09/20/2012 - 08:45:53